Bit-Serial and Digit-Serial GF(2) Montgomery Multipliers using Linear Feedback Shift Registers

نویسندگان

  • M. Morales-Sandoval
  • C. Feregrino-Uribe
  • P. Kitsos
چکیده

This work presents novel multipliers for Montgomery multiplication defined on binary fields GF(2). Different to state of the art Montgomery multipliers, this work uses a Linear Feedback Shift Register (LFSR) as the main building block. We studied different architectures for bit-serial and digit-serial Montgomery multipliers using the LFSR and the Montgomery factors x and xm−1. The proposed multipliers are for different classes of irreducible polynomials: general, all one polynomials (AOP), pentanomials and trinomials. The results show that the use of LFSRs simplifies the design of the multipliers architecture reducing area resources and retaining high performance compared to related works.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Bit-serial and digit-serial GF(2m)Montgomery multipliers using linear feedback shift registers

This work presents novel multipliers for Montgomery multiplication defined on binary fields GF(2). Different to state of the art Montgomery multipliers, this work uses a Linear Feedback Shift Register (LFSR) as the main building block. We studied different architectures for bit-serial and digit-serial Montgomery multipliers using the LFSR and the Montgomery factors x and x. The proposed multipl...

متن کامل

An area/performance trade-off analysis of a GF(2) multiplier architecture for elliptic curve cryptography

A hardware architecture for GF(2 m) multiplication and its evaluation in a hardware architecture for elliptic curve scalar multiplication is presented. The architecture is a parameter-izable digit-serial implementation for any field order m. Area/performance trade-off results of the hardware implementation of the multiplier in an FPGA are presented and discussed. Finite fields like the binary G...

متن کامل

Area/performance trade-off analysis of an FPGA digit-serial GFð2Þ Montgomery multiplier based on LFSR

Montgomery Multiplication is a common and important algorithm for improving the efficiency of public key cryptographic algorithms, like RSA and Elliptic Curve Cryptography (ECC). A natural choice for implementing this time consuming multiplication defined on finite fields, mainly over GFð2Þ, is the use of Field Programmable Gate Arrays (FPGAs) for being reconfigurable, flexible and physically s...

متن کامل

An Area-Efficient GF(2) MSD Multiplier based on an MSB Multiplier for Elliptic Curve LSI

In this paper, we propose an MSD (most significant digit) multiplier based on an MSB (most significant bit) multiplier over GF(2). The proposed multiplier is based on connecting D (digit size)-bit bit-operations in series. In each digit operation in our proposed multiplier, the “left shift and reduction operation” is serially performed for each of D bits. Because registers for storing intermedi...

متن کامل

FPGA accelerated multipliers over binary composite fields constructed via low hamming weight irreducible polynomials

The efficient design of digit-serial multipliers for special binary composite fields, F2nm where gcd(n, m) 1⁄4 1, is presented. These composite fields can be constructed via an irreducible pentanomial of degree nm but not an irreducible trinomial of degree nm. The conventional construction method for such digit-serial multipliers is to exploit the simplicity of pentanomials to obtain efficent l...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2010